The present invention relates to associative memories and methods for operating same, and in particular to a memory cell for use in an associative memory and a method for operating the memory cell.
Increasingly fast memories with correspondingly fast memory cells are required for VLSI microcomputers. An associative memory, such as a content addressable memory (CAM) is commonly utilized in such devices. Such a memory includes a plurality of random access memory (RAM) cells in which information can be written, the information later being compared to subsequent input information. The result of the comparisons is represented by an electronic signal which is utilized for further data processing purposes.
Conventional content addressable memories utilize RAM cells for storing information, the RAM cells in such known memories being connected to relatively complex comparison circuits for the purpose of comparing the stored information to subsequently-received information. Known memory cells which are suitable for use as memory cells in an associate memory thus exhibit many transistor stages and are thus characterized by long delay times in the execution of the necessary memory operations. In view of the relatively large number of components necessary in and with such conventional memory cells, these memory cells require a large amount of wiring or conductor runs in order to be properly connected for use in associative memories.
It is accordingly an object of the present invention to provide a memory cell suitable for use in an associative memory such as a content addressable memory having small delay times by employing only a small number of transistor stages.
Another object of the present invention is to provide an improved memory cell which requires significantly fewer connections and less wiring and/or conductor runs as a result of the employment of a small number of transistor stages.
The above objects are inventively achieved in an improved memory cell which includes a RAM memory cell which is connected to a bit line and a complementary bit line through transistors which have control electrodes connected to a word line. Each output of the RAM cell is also cross-connected to the control electrodes of additional transistors which are connected to the bit lines and which have a common terminal connected to the control electrode of a transistor which determines the state of a hit line. When the word line is activated, the information supplied by the bit line is written into the RAM cell. Information supplied by the bit line when the word line is non-activated is compared with the information currently stored in the RAM cell and the result of the comparison is supplied to the control electrode of the transistor which is utilized to determine the state of the hit line for updating the status of the hit line.
The improved memory cell disclosed and claimed herein, because of the small number of transistors necessary to operate the cell in combination with the various lines associated with the memory, exhibits significantly decreased delay times in comparison with conventional memory cells and further requires a significantly less number of connections for operation.
Only two delay times occur in the memory cell disclosed and claimed herein between the time that information to be compared to the memory content is supplied to the memory cell and the time of transfer of the result of the comparison to the hit line, because only two transistor stages are addressed during execution of this operation.